1. Field of the Invention
The present invention relates to an I/Q demodulation circuit as is incorporated in a digital broadcast reception apparatus or the like for the purpose of converting a radio- or intermediate-frequency signal into a predetermined base band I/Q signal.
2. Description of Related Art
When a radio-frequency signal (hereinafter referred to as an RF signal) or an intermediate-frequency signal (hereinafter referred to as an IF signal) is converted into a baseband signal, it is quite likely that a DC offset (an unnecessary DC component that is produced by the leaking output of a local oscillator, variations among individual devices, and the like) is superimposed on the baseband signal. There have conventionally been known mixer circuits that can eliminate such a DC offset (for example, see Japanese Patent Application Laid-Open No. H 10-303649).
FIG. 15 is a block diagram showing the configuration of a principal portion of the mixer circuit disclosed in Japanese Patent Application Laid-Open No. H10-303649. In the mixer circuit shown in this figure, a mixer 2 multiplies an RF or IF signal fed thereto from an input terminal 1 by a local oscillation signal fed thereto from a local oscillator 3, and outputs the multiplication result to an analog-to-digital converter 6 (hereinafter referred to as the A/D converter 6). Between the terminals 4 and 5 of the local oscillator 3, a resonator is externally connected. The oscillation frequency of the local oscillator 3 is so controlled that the multiplication operation performed by the mixer 2 yields a baseband signal having a desired frequency. The A/D converter 6 converts the baseband signal fed thereto into a digital signal, and feeds it out of the mixer circuit via an output terminal 9. The digital baseband signal produced by the A/D converter 6 is also fed to an averaging circuit 7. The averaging circuit 7 detects the average value of the DC offset amount of the digital baseband signal, and outputs it to a sample-and-hold circuit 8 (hereinafter referred to as the S/H circuit 8) provided in the following stage. The S/H circuit 8 reads and holds the average value of the DC offset amount with predetermined timing, and controls the mixer 2 in such a way as to cancel the voltage difference between the average value of the DC offset amount and the design value of the DC offset amount of the mixer 2.
It is true that, with the mixer circuit configured as described above, it is possible to eliminate the DC offset in the digital baseband signal without providing a high-capacitance coupling capacitor in the stage preceding the output terminal 9. This helps reduce the circuit scale.
However, the mixer circuit configured as described above has the following disadvantages. The mixer circuit is so configured that the DC offset amount is measured during a reception operation and is corrected for according to the thus measured value. Thus, the first disadvantage is that the offset is corrected for with a delay at least equal to one period (which is the time required to find the DC average value of the digital baseband signal). In an I/Q demodulator, the demodulation accuracy depends heavily not only on the DC offset but also on the phase offset of an I/Q signal. However, in the mixer circuit configured as described above, no consideration whatever is given to the correction of the phase offset. Thus, the second disadvantage is that applying the prior art intact to an I/Q demodulator does not contribute to satisfactorily enhancing the demodulation accuracy thereof.